This application claims the priority benefit of Japanese Patent Application No. 11-309541, filed Oct. 29, 1999, the entire disclosure of which is incorporated herein of reference.
1. Field of the invention
The invention relates to a buffer circuit, which is used as an output buffer or a clock buffer of a semiconductor integrated circuit (IC).
2. Description of the Related Art
Details of a prior buffer circuit is disclosed in a Japanese translation by Kanno and Sakaki of the first edition of xe2x80x9cAn Introduction to VLSI Systemxe2x80x9d at pages 21-22, authored by C. Code and L. Conway, and published by Baifukan on Jun. 30, 1981. FIG. 2 is a circuit diagram of a buffer circuit 100 that is illustrated in the above-mentioned publication.
Generally, a GaAs MES FET is widely used in ICs as a Schottky gate FET because of its characteristics of high speed and high integration. The buffer circuit 100 shown in FIG. 2 is used in an output part of an IC having GaAs MES FETs, and outputs a binary operation signal Sout, which corresponds to an input signal Sin applied from an internal circuit of the IC, to an unillustrated circuit connected to a output terminal OUT The buffer circuit 100 include two enhancement type FETs 1, 3 and two depletion type FETs 2, 4 an input terminal IN and the output terminal OUT. The gate of the FET 1 is connected to the input terminal IN which receives the input signal Sin, and the source is connected to ground GND.
The source and the gate of the FET 2 are connected to the drain of the FET 1 at a voltage setting node N1, and the drain is connected to a power supply voltage VD. The FET 2 acts as a load element against the FET 1.
The gate of the FET 3 is connected to the node N1, and the source of the FET 3 is connected to ground GND. The drain of the FET 3 is connected to the output terminal OUT.
The source of the FET 4 is connected to the drain of the FET 3, and the drain of the FET 4 is connected to the power supply voltage VD. Since the gate of the FET 4 is connected to the input terminal IN, the condition of a current path in the FET 4 is 1s changed in response to the voltage of the input signal Sin.
The operation of the buffer circuit 100 shown in FIG. 2 is explained below. As an initial status, when the voltage level of the input signal Sin at the input terminal IN is at an L (low) level, the FET 1 is in a first condition that the current is not easily passed through a transistor because a high resistance value is applied between the source and drain of the FET 1. On the other hand, the FET 2 is in a second condition that the current is easily passed through a transistor because a low resistance value is applied between the source and drain of the FET 2. Therefore, the voltage level at the node N1 is the supply voltage level approximately. Further, since a resistance value between the source and drain of the FET 3 becomes lower, the FET 3 is in the second condition. Moreover, since a resistance value between the source and drain of the FET 4 becomes lower in response to the low level input signal Sin, the FET 4 is in the second condition. However, comparing the resistance value of the FET 3 with that of the FET 4, the resistance value of the FET 3 is lower than that of the FET4. Therefore, since the output terminal OUT is electrically connected to ground GND, the voltage level of the operation signal Sout at the output terminal OUT is at the L level.
When the voltage level of the input signal Sin is changed from the L level to the H (high) level, the FET 1 becomes the second condition, and the current is more easily passed through the FET 4 because its resistance value becomes lower in response to the H level input signal Sin. Since the voltage at the node N1 begins to fall when the FET 1 is in the second condition, the gate voltage of the FET 3 also begins to fall. Further, since the output terminal OUT is electrically connected to the power supply voltage VD through the FET 4 when the current is more easily passed through the FET 4, the voltage at the output terminal OUT begins to rise. When the voltage at the node N1 becomes less than the threshold voltage of the FET 3, the FET 3 is in the first condition. Then, since the rise in the voltage at the output terminal OUT is accelerated, the voltage level of the output terminal OUT rises to the H level. Therefore, the operation signal Sout having the H level is output from the output terminal OUT
Then, when the voltage level of the input signal Sin is changed from the H level to the L level, the FET 1 becomes the first condition, and the current is not easily passed through the FET 4 again. Since the voltage at the node N1 begins to rise when the FET 1 is in the first condition, the gate voltage of the FET 3 also begins to rise. Further, the output terminal OUT is electrically disconnected from the power supply voltage VD when the current is not easily passed through the FET 4. When the voltage at the node N1 exceeds the threshold voltage of the FET 3, the FET 3 becomes the second condition. Then, since the output terminal OUT is electrically connected to ground GND through the FET 3, the voltage level of the output terminal OUT falls to the L level. Therefore, the operation signal Sout having the L level is output from the output terminal OUT.
In the buffer circuit shown in FIG. 2, when a large voltage amplitude of the operation signal Sout should be obtained, it has been considered to apply a high voltage to the gate of the FET 4 in order to increase the conductance of the FET 4. However, the voltage of the input signal Sin that indicate the H level, which is applied to the gate of the FET 4, is clamped at about 0.7 V, which voltage is determined by a current that flows from the gate of the FET 1 to ground GND through the source of the FET 1. In this buffer circuit, since it is difficult to apply a high voltage to the gate of the FET 4, the desirable voltage amplitude can not be obtained. Therefore, to obtain an operation signal Sout with a large voltage amplitude, the width of the FET 3 should be adjusted. However, other problems, for example, circuit design restrictions may occur.
An objective of the invention is to resolve the above-described problem and to provide a buffer circuit, which outputs an operation signal having a large voltage amplitude.
The objective is achieved by a buffer circuit having an input and output terminals, which includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.